1.3.2. Processor Options¶

Instruct the compiler to generate code for the Arm processor variant indicated by , where can be:

1.3.2.2. Select Architecture¶

Instruct the compiler to generate code for the Arm architecture variant indicated by , where can be:

thumbv6m - appropriate for -mcpu=cortex-m0 or -mcpu=cortex-m0plus
thumbv7m - appropriate for -mcpu=cortex-m3
thumbv7em - appropriate for -mcpu=cortex-m4
thumbv8m.main - appropriate for -mcpu=cortex-m33
thumbv8.1-m.main+cdecp0 - can be used to enable CDE intrinsics on a Cortex-m33 device that is equipped with a coprocessor that can execute CDE instructions. See Custom Datapath Extension (CDE) Intrinsics for more information.
armv7r - appropriate for -mcpu=cortex-r4 or -mcpu=cortex-r5 with -marm and -mlittle-endian
armebv7r - appropriate for -mcpu=cortex-r4 or -mcpu=cortex-r5 with -marm and -mbig-endian
thumbv7r - appropriate for -mcpu=cortex-r4 or -mcpu=cortex-r5 with -mthumb and -mlittle-endian
thumbebv7r - appropriate for -mcpu=cortex-r4 or -mcpu=cortex-r5 with -mthumb and -mbig-endian

1.3.2.3. Select Instruction Set¶

Instruct the compiler to generate THUMB mode instructions (16-bit THUMB or T32 THUMB depending on which processor variant is selected) for current compilation; default for Cortex-M type architectures

Instruct the compiler to generate ARM mode instructions for current compilation; default for Cortex-R series processors

1.3.2.4. Select Floating-Point ABI/Coprocessor¶

Instruct the compiler to generate code in accordance with the floating-point ABI indicated by , where can be:

hard - assume floating=point hardware (FPU) is available; pass floating-point type arguments and return values in FPU registers; generate FPU instructions for floating-point type operations
soft - assume no floating-point hardware is available; pass arguments and return values in general-purpose registers (GPRs); perform floating-point operations in software with CPU instructions or in calls to runtime support library functions.

Instruct compiler to use floating-point hardware (FPU) registers and instructions to perform floating-point operations; select the FPU specified by , where can be:

vfpv3-d16 - available in combination with -mcpu=cortex-r4 or -mcpu=cortex-r5
fpv4-sp-d16 - available in combination with -mcpu=cortex-m4
fpv5-sp-d16 - available in combination with -mcpu=cortex-m33

1.3.2.5. Select Endianness¶

-mlittle-endian , -EL ¶

Instruct the compiler to generate little-endian object code; default

Instruct the compiler to generate big-endian object code; only applicable for Cortex-R series processors